Description
Ixia LM622MR 2-Port ATM/PACKET over Sonet Load Module with the following:
- 1 x ATM Load Module with Dual OC3OC12PHY Single-port OC-3/OC-12 PHY module
Ixia’s OC3OC12PHY Ixia LM622MR 2-Port ATM/PACKET over Sonet Load Module OC-3c/OC-12c Load Module is a comprehensive tool for testing network elements with Packet Over SONET/SDH interfaces operating at the STS-3c/STM-1 and STS-12c/STM-4 levels. The Load Module offers full wire-speed packet generation and can be optionally configured to support ATM; this mode of operation is covered in the Asynchronous Transfer Mode (ATM) Load Module data sheet. The Ixia OC-3c/OC-12c Load Module supports multiple physical interfaces via modular PHYs, multiple signal rates, and multiple technologies (ATM and POS), providing a very high level of flexibility in a single module. With a RISC CPU per port running Linux, the module provides a powerful platform for running test applications, including IxNetwork, IxScriptmate, and IxChariot
- Ports Per Load Module : 2 ports per module, each may be populated with different physical interface options
- Connector Type : Dual SC with 1310 nm multi-mode optics or Dual LC using SFP transceiver
- Processor/Memory (per port) : 1392 MIPS PowerPC/256 Mbytes
- Layer 2 Encapsulation : Point-to-Point Protocol (PPP) over SONET/SDH as per RFC 2615, Cisco HDLC, Frame Relay, Cisco Frame Relay, and User-Defined Header
- PPP : Complete LCP, IPCP, OSICP, and MPLSCP Negotiation
- Scrambling : 1+X43 payload scrambling
- Number of Streams : 256 (Packet Stream mode) or 160 (Advanced Stream Scheduler mode)
- Transmit Engine : Built-in FPGA logic for wire-speed packet generation with timestamps, sequence numbers and packet group signatures. Five User-Defined Fields (UDFs)
- Receive Engine : Built-in FPGA logic for wire-speed packet filtering, capturing, real-time latency for each packet group, data integrity, and sequence checking
- Capture Buffer (per port) : 8 MBytes
- Traffic Types : Full Multilayer (IP, TCP, UDP, IGMP, ICMP, RIP, DHCP) performance traffic generation at full wire-speed
- SONET Statistics : Link State, Line Speed, Section LOS, Section LOF, Section BIP (B1), Line AIS, Line RDI, Line REI (FEBE), Line BIP (B2), Path AIS, Path RDI, Path REI (FEBE), Path BIP (B3), Path LOP, Path PLM (C2), Loss of Cell Delineation (LOC)
- TCP/IP Statistics : IP Packets Received, IP Checksum Errors, UDP Packets Received, UDP Checksum Errors, TCP Packets Received, TCP Checksum Errors
